// ------------------------------------------------------------------
// File_name: AndOr.v
// Function : Combinational logic using & and |.
// ------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-06-28
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// ------------------------------------------------------------------

// module header may includes:
// moudle name, port direction, port width and port types

// and , or, not, xor : primitives
module AndOr (
  output X, Y,     // width:1bit, type: wire by default 
  input  A, B, C
  // inout
);

  // '#' means delay (timing)
  // 10 `timescale 1ns/100ps
  // assign : connectivity : wire (reg)

  // assign X = #10 A & B;

  // RTL coding style: ignore # delay non-synthezable
  // and u_and (X, A, B);  // gate-level 
  // or  u_or  (Y, B, C);

  assign #10 X = A & B; // countinous assignment statement: parallel

  assign #10 Y = B | C; // describe combinational circuits

endmodule
